Satvik Maurya

About Me

I am a Ph.D. candidate at the University of Wisconsin-Madison, advised by Prof. Swamit Tannu. I completed my undergraduate studies at Delhi Technological University where I was advised by Prof. Neeta Pandey. Prior to starting grad school, I was an R&D Engineer at Synopsys, Inc. where I designed protocol transactors used for hardware emulation.

Outside of research, I enjoy biking, gaming (I love playing Counter-Strike), reading (I enjoy fantasy books and crime thrillers), music (I have been playing the guitar since I was 13 and I also –try– to sing). I also enjoy cooking, I can cook the North Indian dish called Dal Makhani very well.

Research Interests

Quantum Control Hardware: Qubit control and readout architectures.
FPGA accelerators: Using FPGAs for accelerating datacenter networks.
High Performance Computing

News

[March 2025] Our work on synchronization for fault-tolerant quantum computers has been accepted at ISCA 2025!
[February 2025] Our work on multi-level readout classifiers has been accepted at DAC 2025.
[January 2025] I will be returning to IBM Research for the summer of 2025.
[July 2024] Our work on side-channel attacks via readout crosstalk has been accepted at QCE 2024.
[April 2024] I have been selected to attend the Heidelberg Laureate Forum in Germany!
[December 2023] I will be interning in the quantum hardware team at IBM Research in the Summer of 2024!
[May 2023] A patent application I worked on at AMD Research (Event-Triggered Dynamic Power Management) has been submitted to the USPTO!
[March 2023] Our paper HERQULES was accepted at ISCA 2023!

Publications

ISCA

Synchronization for Fault-Tolerant Quantum Computers

Satvik Maurya, Swamit Tannu

International Symposium on Computer Architecture (ISCA), 2025
DAC

Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout

Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu

Design Automation Conference (DAC), 2025

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QCE

Understanding Side-Channel Vulnerabilities in Superconducting Qubit Readout Architectures

Satvik Maurya, Chaithanya Naik Mude, Benjamin Lienhard, Swamit Tannu

2024 IEEE Conference on Quantum Computing and Engineering (QCE), 2024

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ISCA

Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures

Satvik Maurya, Chaithanya Naik Mude, William D. Oliver, Benjamin Lienhard, Swamit Tannu

International Symposium on Computer Architecture (ISCA), 2023.

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AMD GTAC

Making a Case for Heterogeneous Workload Tests for More Robust Dynamic Power Management

Satvik Maurya, Heather Hanson, Yasuko Eckert, Raj Desikan

AMD Global Technical Authors Conference (GTAC), 2022.
MICRO

COMPAQT: Compressed Waveform Memory Architecture for Scalable Qubit Control

Satvik Maurya, Swamit Tannu

International Symposium on Microarchitecture (MICRO), 2022.

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MWSCAS

Hardware/Software Co-Design of a High-Speed Othello Solver

Pranav Gangwar, Satvik Maurya, Shubham Garg, Sakshi Goyal, Aditya S Kumar, Preyesh Dalmia, Neeta Pandey

International Midwest Symposium on Circuits and Systems (MWSCAS), 2019.

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