About Me

I am a Ph.D. candidate at the University of Wisconsin-Madison, advised by Prof. Swamit Tannu. Prior to starting grad school, I was an R&D Engineer at Synopsys, Inc. where I designed protocol transactors used for hardware emulation. I completed my undergraduate studies at Delhi Technological University where I was advised by Prof. Neeta Pandey.

Outside of research, I enjoy biking, gaming (I love playing Counter-Strike), reading (I enjoy fantasy books and crime thrillers), music (I have been playing the guitar since I was 13 and I also --try-- to sing). I also enjoy cooking, I can cook the North Indian dish called Dal Makhani very well.

Research Interests

  • Quantum Control Hardware: Qubit control and readout architectures.
  • FPGA accelerators: Using FPGAs for accelerating datacenter networks.
  • High Performance Computing

News

  • [August 2025] decoder-bench has been accepted at IISWC 2025.
  • [March 2025] Our work on synchronization for fault-tolerant quantum computers has been accepted at ISCA 2025!
  • [February 2025] Our work on multi-level readout classifiers has been accepted at DAC 2025.
  • [January 2025] I will be returning to IBM Research for the summer of 2025.
  • [July 2024] Our work on side-channel attacks via readout crosstalk has been accepted at QCE 2024.
  • [April 2024] I have been selected to attend the Heidelberg Laureate Forum in Germany!

Publications

IISWC

decoder-bench: Benchmarking Decoders for Quantum Error Correction
IEEE International Symposium on Workload Characterization (IISWC), 2025
Satvik Maurya, Joshua Viszlai, Nithin Raveendran, Poulami Das, Swamit Tannu
PDF • Code

ISCA

Synchronization for Fault-Tolerant Quantum Computers
International Symposium on Computer Architecture (ISCA), 2025
Satvik Maurya, Swamit Tannu
PDF • Code • BibTeX

DAC

Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout
Design Automation Conference (DAC), 2025
Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu
PDF • BibTeX

QCE

Understanding Side-Channel Vulnerabilities in Superconducting Qubit Readout Architectures
IEEE Conference on Quantum Computing and Engineering (QCE), 2024
Satvik Maurya, Chaithanya Naik Mude, Benjamin Lienhard, Swamit Tannu
PDF • BibTeX

ISCA

Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures
International Symposium on Computer Architecture (ISCA), 2023
Satvik Maurya, Chaithanya Naik Mude, William D. Oliver, Benjamin Lienhard, Swamit Tannu
PDF • Code • BibTeX

AMD GTAC

Making a Case for Heterogeneous Workload Tests for More Robust Dynamic Power Management
AMD Global Technical Authors Conference (GTAC), 2022
Satvik Maurya, Heather Hanson, Yasuko Eckert, Raj Desikan

MICRO

COMPAQT: Compressed Waveform Memory Architecture for Scalable Qubit Control
International Symposium on Microarchitecture (MICRO), 2022
Satvik Maurya, Swamit Tannu
PDF • BibTeX

MWSCAS

Hardware/Software Co-Design of a High-Speed Othello Solver
International Midwest Symposium on Circuits and Systems (MWSCAS), 2019
Pranav Gangwar, Satvik Maurya, Shubham Garg, Sakshi Goyal, Aditya S Kumar, Preyesh Dalmia, Neeta Pandey
PDF • BibTeX

Awards

Service

Outreach

Program Committee

Artifact Reviewer

Countries I have been to